1. Field of the Invention
The present invention relates generally to semiconductor devices, methods of manufacturing the same, capacitor structures, and methods of manufacturing the same, and more particularly to a semiconductor device having a semiconductor chip and an interposer including a capacitor and a through via, a method of manufacturing the same, a capacitor structure, and a method of manufacturing the same.
2. Description of the Related Art
Electronic apparatuses are now becoming more sophisticated with more functions in the fields of personal computers, cellular phones, and other mobile equipment.
In order to prevent malfunction due to switching noise in a large-scale integrated circuit (LSI) that operates at high frequencies, a method of reducing source impedance by connecting a decoupling capacitor absorbing noise in parallel with a power supply is employed.
Source impedance Z is expressed by:Z(P)∝V/(nif),  (1)where V is supply voltage, n is the number of elements per LSI, i is the switching current of an element, and f is a driving frequency.
Because of lower LSI voltage, high element integrity, and higher frequencies, there has been a sharp reduction in required impedance. The impedance Z(C) of a decoupling capacitor is given by:Z(C)=[R2+{2πfL−(1/2πfC)}2]1/2,  (2)where R is resistance, L is inductance, and C is capacitance. In order to reduce the impedance of a decoupling capacitor, it is desired to increase capacitance C and reduce inductance L.
Normally, a multilayer ceramic capacitor is disposed around an LSI as a decoupling capacitor. The multilayer ceramic capacitor has electrode layers and ceramic dielectric layers stacked alternately on each other, and has a pair of surface electrodes formed on corresponding side surfaces thereof so that each surface electrode is connected to every other corresponding electrode layer. A large capacitance can be provided, but it is not easy to reduce inductance because the electrode layers are connected to the surface electrodes on the side surfaces.
As the operating frequencies of LSIs become higher, the decoupling capacitor is required to have lower inductance. However, it is difficult to meet this requirement with multilayer ceramic capacitors.
Accordingly, in order to reduce the line length between the LSI and the decoupling capacitor, a method of providing decoupling capacitors 505 formed of thin film capacitors on the surface of an interposer 502 in which through vias 508 are formed in a Si substrate 503 as illustrated in FIG. 1 is proposed (for example, Japanese Laid-Open Patent Application No. 2004-193614).
This method is effective in high-performance LSIs. This is because the interposer 502 employs the Si substrate 503 formed of the same material as the LSI, so that there is no occurrence of problems resulting from stress due to a difference in thermal expansion. This is also because this method responds to an increase in LSI size, finer pitches, and a decrease in strength due to a low-k LSI interconnection insulating film.
FIG. 1 is a cross-sectional view of a conventional semiconductor device 500. As illustrated in FIG. 1, the semiconductor device 500 includes a semiconductor chip 501 that is operated at high frequencies and the interposer 502 to which the semiconductor chip 501 is connected.
The interposer 502 includes the Si substrate 503, the decoupling capacitors 505, an insulating film 507, the through vias 508, and external connection terminals 509. The decoupling capacitors 505, each formed of a lower electrode, a dielectric film, and an upper electrode, are formed on the Si substrate 503. The decoupling capacitors 505 are connected to some of the through vias 508 connected to the power supply electrode pads of the semiconductor chip 501 and the other through vias 508 connected to the ground electrode pads of the semiconductor chip 501. The decoupling capacitors 505 cancel noise generated by the semiconductor chip 501 operating at high frequencies.
Through holes 504 for forming the through vias 508 are formed in the Si substrate 503. The insulating film 507 is formed on the through holes 504. The insulating film 507 isolates the through vias 508 from the Si substrate 503. In general, a thermal oxide film is used for the insulating film 507.
The through vias 508 are formed in the through holes 504. The external connection terminals 509 for connection to a circuit board are formed at the lower end part of the through vias 508 (for example, Japanese Laid-Open Patent Application No. 2004-193614).
In the case of manufacturing this semiconductor device 500, the decoupling capacitors 505 are formed on the Si substrate 503 after forming the through holes 504 and the through vias 508 in the Si substrate 503.
For related art, Japanese Laid-Open Patent Application Nos. 2000-323845, 2004-71589, 2004-95638, 2003-197463, and 2004-273825 may also be referred to.
However, the thickness of the Si substrate 503 of the conventional interposer 502 is greater than or equal to 0.5 mm. Accordingly, the aspect ratio of the through holes 504, that is, the thickness of the Si substrate 503/the diameter of the through holes 504, is high. In order to form these through holes 504, it is necessary to use ICP (Induction Coupling Plasma), which causes the problem of an increasing manufacturing cost of the semiconductor device 500. If the pitch of the external connection terminals 509 of the semiconductor chip 501 becomes narrower in the future, it becomes more difficult to form the through vias 504.
Further, conventionally, the decoupling capacitors 505 formed of thin film capacitors are formed on the Si substrate 503 after forming the through holes 504. This causes a problem in that the decoupling capacitors 505 are likely to be poorly isolated, thus resulting in a reduced yield.
Further, since there is a limit to the capacitance of a thin film capacitor with a single layer structure, it is desirable to increase capacitance by providing a thin film capacitor with a multilayer structure. However, this results in the problem of higher costs because electrodes and a dielectric film are formed and patterned for each layer. Further, since the thin film capacitor is formed on a patterned uneven underlayer, there is a problem in that a poor yield rate due to unevenness of the film thickness of a dielectric film and to dust causes an increase in costs.